library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.ALU_components_pack.all;

entity ALU is
	Port(
		rst         : in  std_logic;
		counter_rst : in  std_logic;
		A           : in  std_logic_vector(7 downto 0);
		B           : in  std_logic_vector(7 downto 0);
		FN          : in  STD_LOGIC_VECTOR(2 downto 0);
		result      : out STD_LOGIC_VECTOR(7 downto 0);
		overflow    : out STD_LOGIC;
		sign        : out STD_LOGIC
	);
end ALU;

architecture Structural of ALU is
	component Arithmetic
		port(
			A_arithmetic        : in  std_logic_vector(7 downto 0);
			B_arithmetic        : in  std_logic_vector(7 downto 0);
			FN_arithmetic       : in  STD_LOGIC_VECTOR(2 downto 0);
			result_arithmetic   : out STD_LOGIC_VECTOR(7 downto 0);
			overflow_arithmetic : out STD_LOGIC;
			sign_arithmetic     : out STD_LOGIC);
	end component Arithmetic;
	signal A_arithmetic   : std_logic_vector(7 downto 0);
	signal B_arithmetic   : std_logic_vector(7 downto 0);
	signal FN_arithmetic  : std_logic_vector(2 downto 0);
	signal result_arith   : std_logic_vector(7 downto 0);
	signal overflow_arith : std_logic;
	signal sign_arith     : std_logic;
	signal resultMax      : std_logic_vector(7 downto 0);

-- Signals here if needed.


begin
	DUT : Arithmetic
		port map(A_arithmetic        => A,
			     B_arithmetic        => B,
			     FN_arithmetic       => FN,
			     result_arithmetic   => result_arith,
			     overflow_arithmetic => overflow_arith,
			     sign_arithmetic     => sign_arith
		);

	-- Develope the structure of the ALU here. 

	process(A, B, FN)
	begin
		if (A > B) then
			resultMax <= A;
		else
			resultMax <= B;
		end if;

	end process;
	result   <= resultMax when (FN = "100") else result_arith;
	overflow <= '0' when (FN = "100") else overflow_arith;
	sign     <= '0' when (FN = "100") else sign_arith;

end Structural;
